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TEA5040S
WIDE BAND VIDEO PROCESSOR
. . . . . . . .
DIGITAL CONTROL OF BRIGHTNESS, SATURATION AND CONTRAST ON TV SIGNALS AND R, G, B INTERNAL OR EXTERNAL SOURCES BUS DRIVE OF SWITCHING FUNCTIONS DEMATRIXING OF R, G, B SIGNALS FROM Y, R-Y, B-Y, TV MODE INPUTS MATRIXING OF R, G, B SOURCES INTO Y, R-Y, B-Y SIGNALS AUTOMATIC DRIVE AND CUT-OFF CONTROLS BY DIGITAL PROCESSING DURING FRAME RETRACE PEAK AND AVERAGE BEAM CURRENT LIMITATION ON-CHIP SWITCHING FOR R, G, B INPUT SELECTION ON-CHIP INSERTION OF INTERNAL OR EXTERNAL R, G, B SOURCES
DESCRIPTION The TEA5040S is a serial bus-controlled videoprocessing device which integrates a complex architecture fulfilling multiple functions.
SDIP42 (Plastic Package) ORDER CODE : TEA5040S
PIN CONNECTIONS
VCC
R INTERNAL INPUT R EXTERNAL INPUT G INTERNAL INPUT G EXTERNAL INPUT B INTERNAL INPUT B EXTERNAL INPUT FB EXTERNAL INPUT FB INTERNAL INPUT B-Y INPUT R-Y INPUT Y INPUT CLOCK DATA ENABLE VOLTAGE REFERENCE R CLAMP MEMORY 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 SWITCHABLE VIDEO OUTPUT SYNCHRO INPUT INTERNAL VIDEO OUTPUT INTERNAL VIDEO INPUT AVERAGE BEAM LIMIT. REF EXTERNAL VIDEO INPUT
AVERAGEBEAMCURRENTFILTER
LEAKAGE CURRENT FILTER CATHODE CURRENT INPUT SWITCH CUT-OFF RESISTANCE SUPER SANDCASTLE INPUT B OUTPUT
CUT-OFFMEMORY (B CHANNEL)
DRIVE MEMORY (B CHANNEL) G OUTPUT CUT-OFF MEMORY (G CHANNEL) DRIVE MEMORY (G CHANNEL) R OUTPUT CUT-OFF MEMORY (R CHANNEL) DRIVE MEMORY (R CHANNEL) NOT TO BE CONNECTED
5040S-01.EPS
G CLAMP MEMORY
B CLAMP MEMORY GROUND NOT TO BE CONNECTED
April 1993
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TEA5040S
BLOCK DIAGRAM
V REF VIDEO INT EXT OUT 37 40 DATA EN 15 CLK 13 36
39
32
14
38
INT SYNC.
41
VIDEO SWITCH
42
DELAY T IME
SUPE R SAND CASTLE DETECTOR
BUS DECODER
BEA M CURRENT LIMIT
LOGIC
Y
12
(R - Y) 11 (B - Y) 10
R R' G G' B B'
2 3 4 5 6 7
R Y MATRIX G
CONTRAST
BRIGHTNESS
Y
25 R OUT
BLACK LEVEL CONTROL MATRIX
SAT . (R - Y)
(R - Y)
28 GOUT
B (B - Y) SAT .
(B - Y)
31 B OUT
1 X3 + 12V
23 X3
24
33
34
CATHODE CURRENTS DRIVE MEMORIES CUT OFF MEMO RIES
GENERAL DESCRIPTION Brief Description This integrated circuit incorporates the following features : - a synchro and two video inputs - a fixed video output - a switchable video output - normal Y, R-Y, B-Y TV mode inputs - double set of R, G, B inputs - brightness, contrast and saturation controls as well on a R, G, B picture as on a normal TV picture - digital control inputs by means of serial bus - peak beam current limitation - average beam current limitation - automatic drive and cut-off controls Block Diagram Description BUS DECODER A 3 lines bus (clock, data, enable) delivered by the microcontroller of the TV-set enters the videoprocessor integrated circuit (pins 13-14-15). A control system acts in such a way that only a 9-bit word is taken intoaccount by the videoprocessor. Six of the bits carry the data, the remaining three carry the address of the subsystem.
Function Brightness Control Contrast Control Colour on/off Selection Insertion Allowed Sync/Async Mode Int/Ext Video Switching B-Y Saturation Control R-Y Saturation Control Address 0 1 2 3 4 5 6 7 Number of Bits 5 5 1 1 1 1 6 6
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5040S-02.EPS
TEA5040S
Table below depicts 9-bit words required for various functions.
Subsystem's Configuration BRIGHTNESS CONTRAST COLOUR ON/OFF INSERTION SYNC/ASYNC MODE VIDEO INT/EXT SATURATION B-Y SATURATION R-Y Min. Max. Min. max. Off On Allowed Not Allow. Sync. Async. Ext. Int. Min. Max. Min. Max. Data Bits LSB....MSB X00000 X11111 X00000 X11111 XXXXX0 XXXXX1 XXXXX0 XXXXX1 XXXX0X XXXX1X XXXXX0 XXXXX1 000000 111111 000000 1111 Add. Bits LSB....MSB 000 100 010 110 001 101 011 111
A demultiplexer directs the data towards latches which drive the appropriate control. More detailed information about serial bus operation is given in the following chapter. Video Switch The video switch has three inputs : - an internal video input (pin 39), - an external video input (pin 37), - a synchro input (pin 41), and two outputs : - an internal video output (pin 40), - a switchable video output (pin 42) The 1Vpp composite video signal applied to the internal video input is multiplied by two and then appears as a 2Vpp low impedance composite video signal at the output. This signal is used to deliver a 1Vpp/75 composite video signal to the peri-TV plug. The switchable video output can be any of the three inputs. When the Int/Ext one active bit word is high (address number 5), the internal video input is selected. If not, either a regenerated synchro pulse or the external video signal is directed towards this output depending on the level of the Sync/Async one active bit word (address number 4). As this output is to be connected to the synchro integrated circuit, RGB information derived from an external source via the Peri-TV plug can be displayed on the screen, the synchronization of the TV-set being then made with an external video signal. When RGB information is derived from a source integrated in the TV-set, a teletext decoder for example, the synchronization can be made either on the internal video input (in case of synchronous data) or on the synchro input (in case of asynchro-
nous data). R, G, B Inputs There are two sets of R, G, B inputs : one is to be connected to the peri-TV plug (Ext R, G, B), the second one to receive the information derived from the TV-set itself (Int R, G, B). In order to have a saturation control on a picture coming from the R, G, B inputs too, it is necessary to get R-Y, B-Y and Y signals from R, G, B information : this is performed on the first matrix that receives the three 0.9Vp (100% white) R, G, B signals and delivers the corresponding Y, R-Y, B-Y signals. These ones are multiplied by 1.4 in order to make the R-Y and B-Y signals compatible with the R-Y and B-Y TV mode inputs. The desired R, G, B inputs are selected by means of 3 switches controlled by the two fast blanking signal inputs. A high level on FB external pin selects the external RGB sources. The three selected inputs are clamped in order to give the required DC level at the output of this first matrix. The three not selected inputs are clamped on a fixed DC level. Y, R-Y, B-Y Inputs The 2Vpp composite video signal appearing at the switchable output of the video switch (pin 42) is driven through the subcarrier trap and the luminance delay line with a 6 dB attenuation to the Y input (1Vpp ; pin 12). In order to make this 1Vpp (synchro to white) Y signal compatible with the 1Vpp (black to white) Y signal delivered by the first matrix, it is necessary to multiply it by a coefficient of 1.4. R, G, B Insertion Pulse (fast blanking) A R, G, B source has also to provide an insertion
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TEA5040S
pulse. Since this integrated circuit can be directly connected to two different sources, it is necessary then to have two separate insertion pulse inputs (pin 8-9). Fast blanking can be inhibited by a one active bit word. The two fast blanking inputs carry out an OR function to insert R, G, B sources into TV picture. The external fast blanking (FB ext.) selects the appropriate R, G, B source. Controls The four brightness, contrast and saturation control functions are direct digitally controlled without using digital-to-analog converters. The contrast control of the Y channel is obtained by means of a digital potentiometer which is an attenuator including several switchable cells directly controlled by a 5 active bit word (address number 1). The brightness control is also made by a digital potentiometer (5 active bit word, address number 0). Since a + 3dB contrast capability is required, the Y signal value could be up to 0.7Vpp nominal. For both functions, the control characteristics are quasi-linear. In each R-Y and B-Y channel, a six-cell digital attenuator is directly controlled by a 6 active bit word (address number 6 and 7). The tracking neede d to keep the saturation constant when changing the contrast has to be done externally by the microcontroller. Furthermore, colour can be disabled by blankingR-Y and B-Y signals using one active bit word (address number 2) to drive the one-chip colour ON/OFF switch. Second Matrix, Clamp, Peak Clipping, Blanking The second matrix receives the Y, R-Y and B-Y signals and delivers the corresponding R, G, B signals. As it is required to have the capability of + 6dB saturation, an internal gain of 2 is applied on both R-Y and B-Y signals. A low clipping level is included in order to ensure a correct blanking during the line and frame retraces. A high clipping level ensures the peak beam current limitation. These limitations are correct only if the DC bias of the three R, G, B signals are precise enough. Therefore a clamp has been added in each channel in order to compensate for the inaccuracy of the matrix. Sandcastle Detector And Counter The three level supersandcastle is used in the circuit to deliver the burst pulse (CLP), the horizontal pulse (HP), and the composite vertical and horizontal blanking pulse (BLI). This last one is regenerated in the counter which delivers a new
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composite pulse (BL) in which the vertical part lasts 23 lines when the vertical part of the supersandcastle lasts more than 11 lines. The TEA5040S cannot work properly if this minimum duration of 11 lines is not ensured. The counterdelivers different pulses neededcircuit and especially the line pulses 17 to 23 used in the automatic drive and cut-off control system. Automatic Drive And Cut-off Control System Cut-off and drive adjustments are no longer required with this integrated circuit as it has a sample and hold feedback loop incorporating the final stages of the TV-set. This system works in a sequential mode. For this purpose, special pulses are inserted in G, R and B channels. During the lines 17, 18 and 19, a "drive pulse" is inserted respectively in the green, red and blue channels. The line 20 is blanked on the three channels. During the lines 21, 22 and 23, a "quasi cut-off pulse" is inserted respectively in the green, red and blue guns. The resulting signal is then applied to the input of a voltage controlled amplifier. In the final stages of the TV-set, the current flowing in each green, red and blue cathode is measured and sent to the videoprocessor by a current source. The three currents are added together in a resistor matrix which can be programmed to set the ratio between the three currents in order to get the appropriate colour temperature. The output of the matrix forms a high impedance voltage source which is connected to the integratedcircuit (pin 34). Same measurement range between drive and cutoff is achieved by internally grounding an external low impedance resistor during lines 17, 18 and 19. This is due to the fact that the drive currents are about one hundred times higher than the cut-off and leakage currents. Each voltage appearing sequentially on the wire pin 34 is then a function of specific cathode current : - When a current due to a drive pulse occurs, the voltage appearing on the pin 34 is compared within the IC with an internal reference, and the result of the comparison charges or discharges an external appropriate drive capacitor which stores the value during the frame. This voltage is applied to a voltage controlled amplifier and the system works in such a way that the pulse current drive derived from the cathode is kept constant. - During the line 20, the three guns of the picture tube are blanked. The leakage current flowing out of the final stages is transformed into a voltage
TEA5040S
which is stored by an external leakage capacitor to be used later as a reference for the cut-off current measurement. - When a current due to a cut-off pulse occurs, the voltage appearing on the pin 34 is compared within the IC to the voltage present on the leakage memory. An appropriate externalcapacitor is then charged or discharged in such a way that the difference between each measured current and the leakage current is kept constant, and thus the quasi cut-off current is kept constant. Average Beam Current Limitation The total current of the three guns is integrated by means of an internal resistor and an external capacitor (pin 36) and then compared with a programmable voltage reference (pin 38). When 70% of the maximum permitted beam current is reached, the drive gain begins to be reduced ; to do so, the amplitude of the inserted pulse is increased. In order to keep enough contrast, the maximum drive reduction is limited to 6dB. If it is not sufficient, the brightness is suppressed. SPECIFICATION FOR THE THOMSON BI-DIRECTIONAL DATA BUS This is a bi-directional 3-wire (ENABLE, CLOCK, DATA) serial bus. The DATA line transmission is bi-directional whereas ENABLE and CLOCK lines are only microprocessor controlled. The ENABLE and CLOCK lines are only driven by the microcomputer. Figure 1 length. The number is determined while ENABLE is low and by counting the negative clock edges. As soon as the high edge of the ENABLE signal is applied, the number is fixed (see Figure 2). The reply word lenght from any of the IC on the bi-directional line is four bits. If it is found insufficient then the reply word can be expandedto include two repetitive reply sequences one after the other. The bi-directional transmission is enabled if : - the IC has been previously addressed at the positive going edge of the enable pulse. - ENABLE remains high, and DATAis available only during the periodwhen the clock remains low. - number of identification bits : n 1...n : data from the microcomputer - number of bi-directional clocks : 4 1...M : data to the microcomputer The four bit reply word (synchronized with the clock coming from the microcontroller) from the addressed IC to the microcontroller is sent only once. Subsequent clock pulses present on the clock line will be ignored by the IC in question. The data sent to the microcontroller can generally be suppressed completely or partially, but in the case of the videoprocessor, a minimum reply word lenght of 1 has to be maintained (see Figure 3). This implies that a bi-directional bus that incorporates other IC's together with a videoprocessor IC is then also limited by the minimum reply word restriction of 1. The data word from the microcompter is divided into : - addresses within the IC - data The data word to the microcomputer is divided into - two data bits, - two address bits After the operating voltage is applied, the first transmission will be used as a reset command, i.e. the data word will not be detected. - number of identification bits : n 1...n : data from the microcomputer - number of bi-directional clocks : 1 1 : data the microcomputer (which is the minimum number for the videoprocessor)
P
It is possible to select several IC from the microprocessor via the bus. The identification of each particular IC is achieved by the length of the word (number of data bits/clock pulses), meaning that each IC responds with its own particular word
5040S-03.EPS
IC I
IC II
IC III
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TEA5040S
Figure 2
NEW WORD h b ENABLE b
a CLOCK
b
c
b
d
e
f
a
c b b k
DATA
1
2
n g i
I
K
L
M
5040S-04.EPS
Figure 3
h b ENABLE b NEW WORD
a CLOCK
b
c
b
d
e
f
a
c b b k
DATA
1
2
n g i
I
5040S-05.EPS
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TEA5040S
BI-DIRECTIONAL DATA BUS
Symbol a b c d e f g h Parameter Min. 5 0 5 70 N/A N/A N/A new word to same IC new word to other IC Typ. Max. Unit s s s s TIMING Identification nr-9 (9 video processor address) (see figures 2-3)
24 70
ms s
ABSOLUTE MAXIMUM RATINGS TAMB = 25C (unless otherwise noted)
Symbol VCC TOPER TSTG Parameter Supply Voltage Pin 1 Operating Temperature Range Storage Temperature Range
5040S-02.TBL 5040S-04.TBL 5040S-03.TBL
Min. 14
Typ.
Max.
0, + 60 - 25, + 125
Unit V C C
THERMAL DATA
Symbol R th(j-a) Parameter Junction-ambiant Thermal Resistance Typ. Value 60
o
Unit C/W
ELECTRICAL OPERATING CHARACTERISTICS (TAMB = 25C, VCC = 12V, unless otherwise specified)
Symbol VCC ICC Parameter Supply Voltage Pin 1 Supply Current Pin 1 External Video Input (75 source impedance) Signal Amplitude Pin 37 Input Current Pin 37 Internal Video Input (300 source impedance) Signal Amplitude Pin 39 Input Current Pin 39 Synchro Input Output Signal Amplitude Pin 42 (for a 0.5V input signal on pin 41) Internal Video Output Pin 40 Dynamic DC Level (bottom of synchro pulse) Gain between Pin 39 (for 1Vpp on pin 39) and Pin 40 Crosstalk between Pin 37 and Pin 40) Bandwidth (- 1dB) Switchable Video Output Pin 42 Dynamic (pin 37 or pin 39 selected) Gain between Pins 37 and 42 (for 1VPP on pin 37) Gain between Pins 39 and 42 (for 1VPP on pin 39) Crosstalk between Pins 37 or 39 with Pin 42 Bandwidth (- 1dB) Min. 10.8 Typ. 12 80 Max. 12.5 104 Unit V mA
VIDEO SWITCH V37 I37 V39 I39 1 10 1 10 0.5 2.7 1 5 6 2.7 5 5 0.6 1.4 30 1.4 30 Vpp A Vpp A V Vpp V dB dB MHz Vpp dB dB dB MHz 7/12
6
2 7 - 50
7 - 50 - 50
5040S-01.TBL
TEA5040S
ELECTRICAL OPERATING CHARACTERISTICS (continued)
Symbol TV MODE INPUTS Y V12 I12 R-Y V11 I11 B-Y V10 I10 Luminance Input Pin 12 Signal Amplitude (100% white) DC Level (on black level) Input Current R-Y Input Pin 11 Signal Amplitude (75% saturation) DC Level (on black level) Input Current B-Y Input Pin 10 Signal Amplitude (75% saturation) DC Level (on black level) Input Current Signal Amplitude (100% saturation without synchro pulse) DC Level (on black level) Input Current FAST BLANKING INPUTS PINS 8-9 TV/RGB Mode Threshold Switching Time Switching Time Delay CLAMP MEMORY OUTPUT PINS 17-18-19 Voltage Range Input Current REFERENCE PARAMETER VREF Reference Voltage Pin 16 Blanking Threshold Burst Gate Threshold Line Retrace Threshold Input Current Pin 32 Grounded DRIVE AND CUT-OFF MEMORY OUTPUT PINS 23-24-26-27-29-30 Drive Leakage Current Pins 23-26-29 Cut-off Leakage Current Pins 24-27-30 Minimum Active Level Pins 24-27-30 LEAKAGE CURRENT MEMORY OUTPUT PIN 35 Voltage Range Input Current (during picture pin 35 = 5V) Charging Output Impedance Minimum Voltage (pin 34 grounded) CATHODE CURRENTS INPUT PIN 34 0.26 0.35 0.4
5040S-05.TBL
Parameter
Min.
Typ.
Max.
Unit
1 4
1.5 10
Vpp V A Vpp V A Vpp V A Vpp V A V ns ns V A V
1.05 4.7
1.47 2
1.33 4.7
1.86 2
RGB INPUTS PINS 2-3-4-5-6-7 0.7 3.2 1 3 0.5 70 70 8 10 11 2 0.9
4 1 6.4 3.1 1.4 6.9 3.4 1.8 7.6 3.8 100 1 1 4 3 0.5 500 3 10 0.50
SANDCASTLE INPUT PIN 32 V V V A A A V V A V A V V
Output Current during the Line Trace (pin 34 grounded) Voltage during Lines 17, 18, 19 Voltage Difference during Lines 21, 22, 23 and during Line 20
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TEA5040S
ELECTRICAL OPERATING CHARACTERISTICS (continued)
Symbol Parameter Voltage Amplitude on Cathode Currents Input for Drive Decrease Threshold 10% on Drive/cut-off 1V on Pin 38 2V on Pin 38 Voltage Amplitude on Cathode Currents Input for Brightness Decrease Threshold 1V on Pin 38 2V on Pin 38 Saturation Impedance [for 5mA] (open during lines 20, 21, 22, 23) REFERENCE VOLTAGE INPUT FOR THE AVERAGE BEAM CURRENT LIMITER PIN 38 V38 I38 Reference Voltage Input Current (V 38 = 1V) 0 < V34 < 7V RGB OUTPUTS R (PIN 25), G (PIN 28), B (PIN 31) Inserted Levels Low Clipping Level Referred to quasi Cut-off Inserted Level (100% = B/W output signal at maximum contrast with 0.5V (B/W) input Y signal) High Clipping Level Referred to quasi Cut-off Inserted Level (100% = B/W output signal at maximum contrast with 0.5V (B/W) input Y signal) Drive Inserted Level Referred to quasi Cut-off Inserted Level (without beam limitation, V 38 = 6V, V34 grounded) Bandwidth (- 3dB) (TV mode and R, G, B mode) Crosstalk for any of the 11 Inputs Pins 2-3-4-5-6-7-10-11-12-37-39 on any of the 5 Outputs Pins 25-28-31-40-42 (range : DC to 1MHz) Brightness Nominal Brightness Referred to quasi Cut-off Inserted Level (bit word "10000" address = 0) Total Brightness Range (100 % = W/B output signal when 0.5V (W/B) on pin 12 and max. contrast) Maximum Brightness (100% = W/B output signal when 0.5V (W/B) on pin 12 and max. contrast) Minimum Brightness (100% = W/B output signal when 0.5V (W/B) on pin 12 and max. contrast) Differential Brightness between any two Channels (TV mode, colour off, pins 10-11-12 AC grounded, 0.5 (W/B) signal on Pin 12, maximum contrast = 100% on RGB outputs) Variation of the Differential Brightness (in the whole saturation control range (including colour off)) Contrast : Max. Contrast Attenuation Saturation Max. Saturation Max. Saturation Attenuation Colour off Attenuation 45 115 35 10 - 50 % % % MHz dB 0 5 - 20 V V V Min. Typ. Max. Unit CATHODE CURRENTS INPUT PIN 34 (continued) V34 0.7 1.4 1 2 250 V V V V
V34
IMPEDANCE SWITCH PIN 33)
AVERAGE BEAM CURRENT FILTER PIN 36 VOLTAGE RANGE 6
- 25 78 38 - 40 2
% % % % %
0.5 11 6 20 40
% dB
5040S-06.TBL
dB dB dB
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TEA5040S
ELECTRICAL OPERATING CHARACTERISTICS (continued)
Symbol Parameter Output Signal Amplitude Pins 25-28-31 (blanking to high clipping) Y input : 0.7V B/W q 0dB Contrast, Bit Word = 010110, Address = 1 q Maximum Brightness q Maximum Drive Efficiency (Pins 23-26-29 grounded) q No Average Beam Current Limitation (Pin 38 to 6V) Black to White Output Voltage Y Input : 0.5V (B/W) Maximum Contrast (Pin 38 to 6V, Pins 23-26-29 grounded) Drive Efficiency VOUT (Pins 23-26-29 grounded) Ratio : VOUT (Pins 23-26-29 to VCC) (no average beam current limitation Pin 38 to 6V) Black Level Control (variable DC voltage from 4V to VCC on Pins 24-27-30)
q
Min.
Typ. 6.2
Max.
Unit V
RGB OUTPUTS R (PIN 25), G (PIN 28), B (PIN 31) (continued)
3.6
V
3.6
4.3 3.5 1
V V V
5040S-07.TBL
BUS INPUTS PINS 13-14-15 VHL VLL High Level Low Level
10/12
APPLICATION CIRCUIT
Y INT. SYNC
EXT. VIDEO
FB R EXT. EXT.
G EXT.
B EXT.
INT. VIDEO
FB INT.
R INT.
G INT.
B INT.
75
75
75
75
75
75
75
75
75
75
+12V 10F 22nF 8 5 7 39 4 6 17 18 19 3 9 2 22nF 22nF 10F 22nF 22nF 22nF 100nF 100nF 41 37 100nF 33
CONTROL TUBE FEEDBACK
100 34 10F 35 100 31 100 28 100 25 B G R TO VIDEO AMPS
560
100F
40
4.7F
16
Y TO CHROMA AND SYNCHRO
42
TEA5040S
1.2k
10F
D.L.
12
1.2k 11 22nF 10F
1k
10 36 38 1 20 22nF R1
13
14
15
32
23 22nF
26 22nF
29 22nF
24 100nF
27 100nF
30
100nF
B-Y SSC R2
10
R-Y
CK
DATA
En 470F 22nF
V CC
TEA5040S
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5040S-06.EPS
TEA5040S
PACKAGE MECHANICAL DATA 42 PINS - PLASTIC SHRINK DIP
e4 F
a1
A
I
b2
b e3
e
L
b1
Stand-off
E
D
42
22
1
21
Dimensions A a1 b b1 b2 b3 D E e e3 e4 F i L
Min. 3.30
Millimeters Typ. 0.51 0.35 0.20 0.75 0.75 15.57
Max.
Min. 0.130
Inches Typ. 0.020 0.014 0.008 0.030 0.030 0.613
Max.
0.59 0.36 1.42 39.12 17.35 0.070 1.400 0.600
0.023 0.014 0.056 1.540 0.683
1.778 35.56 15.24 14.48 5.08 2.54
0.100
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1994 SGS-THOMSON Microelectronics - All Rights Reserved Purchase of I2C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips. SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
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SDIP42.TBL
0.570 0.200
PMSDIP42.EPS

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